With shrinking size and increasing accuracy of the electronic systems and devices there is an increased requirement of Electro Magnetic Compatibility (EMC). Various standards such as, the Federal Communications Commission (FCC) regulate the Electro Magnetic Interference levels of such devices. These standards like FCC require that the manufacturer measure the performance of the system for certification.
Serial ATA technology uses the Spread Spectrum Clocking (SSC) where low frequency modulation on the transmitter clock signals is performed with respect to time in a controlled manner. The purpose of this modulation is to spread the spectral energy to mitigate the unintentional interference of radio frequency. A typical modulating frequency may be decided based on factors such that, the frequency does not exhibit more energy on certain peaks, and that the frequency does not interfere with PLL frequency of operation, that is, loop-BW and the modulation spreads the spectral energy content to overcome interference with radio frequency (RF).
Usually, spread spectrum clocking involves dealing with three parameters namely, Modulation Scheme, Modulation depth, and Modulation Frequency.
The two most common Modulation Schemes are linear triangle modulation and a non-linear modulation scheme, according to U.S. patent, commonly known as the Hershey Kiss scheme. The Hershey Kiss™ modulation scheme gains better EMI reduction than the linear triangle scheme.
Modulation depth is the amount of frequency modulation applied to the clock carrier. SATA specification requires 0.5% to 1% down spread modulation. Down spread means that the clock carrier is 1.5 GHz is modulated down to 1.5 GHz-1.5 KHz for value of 0.1%.
Modulation frequency is the repetition rate of the modulation scheme applied to the clock carrier signal. The typical modulating frequency is 33.3 KHz (30 KHz to 90 KHz). On certain peaks, this frequency will not have more energy. It does not interfere with PLL frequency of operation that is Loop-BW and modulation spreads the spectral energy content to overcome interference with RF.
Usually at the physical layer developers and the manufacturing units have large number of device under test (DUTs), which need to be tested. For example in case of a serial technology standard Serial ATA (Serial ATA Revision 2.5 27 Oct. 2005) requires vendors to make their DUT compliant. This may require performance of tests, for example performing PHY-TSG-OOB, RxTx, SI and RSG/RM tests. For carrying out these test procedures there is a need for giving an SSC modulated waveform as an stimuli.
The traditional solution setup requires two instruments namely a Bit Pattern Generator and an Function/Waveform generator as shown in FIG. 1.
The signal generated by the Function/Waveform generator 101 is used to modulate the internal clock of the Bit pattern generator 102. This signal provides the desired compression and expansion of the output data stream from the bit pattern generator resulting in the generation of a desired SSC modulated output from bit pattern generator output 102a. 
The three SSC parameters, Modulation scheme, Modulation depth and Modulation Frequency are controlled by the signal generated by the Function/Waveform generator.
However the above system of providing SSC test signal may have various problems associated. The setup is generally complex as the generation of SSC modulated signal needs a Bit pattern generator and Function/Waveform generator. Further, as the data stream of the bit pattern generator is modulated using a signal from the Function/Waveform generator it adds to additional cost to the setup. Also, working with this setup is time consuming, as there is a need to make the systems to work coherently.
Using Agilent BERT, both SSC modulations and Sinusoidal jitter generation cannot be achieved simultaneously.
There is therefore a requirement of a simple yet precise system and method for synthesizing and generating the SSC modulated signal with precision and in a controlled manner.